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lt1719 1 1719fa typical application features description applications l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. ultrafast is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. overdrive (mv) 0 delay (ns) 30 50 1719 ta02 10 20 40 8 7 6 5 4 3 2 1 0 25c v step = 100mv v + = 5v c load = 10pf rising edge (t pdlh ) falling edge (t pdhl ) n ultrafast: 4.5ns at 20mv overdrive 7ns at 5mv overdrive n low power: 4.2ma at 3v n separate input and output power supplies (so-8 only) n output optimized for 3v and 5v supplies n ttl/cmos compatible rail-to-rail output n low power shutdown mode: 0.1a n low pro? le (1mm) sot-23 (thinsot?) package the lt ? 1719 is an ultrafast? comparator optimized for low voltage operation. the input voltage range extends from 100mv below v ee to 1.2v below v cc . internal hysteresis makes the lt1719 easy to use even with slow moving input signals. the rail-to-rail outputs directly interface to ttl and cmos. alternatively the symmetric output drive can be harnessed for analog applications or for easy translation to other single supply logic levels. a shutdown control allows for reduced power consumption and extended battery life in portable applications. the lt1719 is available in the so-8 and 6-lead sot-23 package. the so-8 package has separate supplies which allow ? exible operation, accomodating separate analog input ranges and output logic levels. for a dual/quad comparator with similar performance, see the lt1720/lt1721. n high speed differential line receiver n crystal oscillator circuits n level translators n threshold detectors/discriminators n zero-crossing detectors n high speed sampling circuits n delay lines 2.7v to 6v crystal oscillator with ttl/cmos output propagation delay vs overdrive C + c1 lt1719 2.7v to 6v 2k 620 220 1mhz to 10mhz crystal (at-cut) 2k 1719 ta01 0.1f 1.8k output ground case 4.5ns single/dual supply 3v/5v comparator with rail-to-rail output
lt1719 2 1719fa pin configuration absolute maximum ratings (note 1) order information lead free finish tape and reel part marking package description temperature range lt1719cs8#pbf lt1719cs8#trpbf 1719 8-lead plastic so 0c to 70c lt1719is8#pbf lt1719is8#trpbf 1719i 8-lead plastic so C40c to 85c lt1719cs6#pbf lt1719cs6#trpbf lthw 6-lead plastic tsot-23 0c to 70c lt1719is6#pbf lt1719is6#trpbf ltjf 6-lead plastic tsot-23 C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ supply voltage +v s to gnd (lt1719s8) ........................................ 7v v cc to v ee (lt1719s8) ........................................ 12v +v s to v ee (lt1719s8) ....................................... 12v v ee to gnd (lt1719s8) ....................... C12v to 0.3v v + to v C (lt1719s6) ...............................................7v input current (+in, Cin or shdn) ...................... 10ma output current (continuous) ........................... 20ma operating temperature range c-grade .................................................. 0c to 70c i-grade ............................................... C40c to 85c junction temperature ......................................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................. 300c top view +v s out shdn gnd v cc +in Cin v ee s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 + C Cin 1 v C 2 +in 3 6 shdn 5 out 4 v + top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 110c/w t jmax = 150c, ja = 230c/w
lt1719 3 1719fa electrical characteristics symbol parameter conditions min typ max units v cc C v ee input supply voltage (lt1719s8 only) l 2.7 10.5 v +v s output supply voltage (lt1719s8 only) l 2.7 6 v v + C v C supply voltage (lt1719cs6 only) l 2.7 6 v v cmr input voltage range (note 2) (lt1719s8) (lt1719s6) l l v ee C 0.1 v C C 0.1 v cc C 1.2 v + C 1.2 v v v trip + v trip C input trip points (note 3) l l C1.5 C5.5 5.5 1.5 mv mv v os input offset voltage (note 3) l 0.4 2.5 3.5 mv mv v hyst input hysteresis voltage (note 3) l 2.0 3.5 7 mv v os /t input offset voltage drift l 10 v/c i b input bias current l C6 C2.5 0 a i os input offset current l 0.2 0.6 a cmrr common mode rejection ratio (note 4) (lt1719s8) (note 5) (lt1719s6) l l 55 55 70 65 db db psrr power supply rejection ratio (note 6) (lt1719s8) (note 7) (lt1719s6) 65 65 80 80 db db a v voltage gain (note 8) v oh output high voltage i source = 4ma, v in = v trip + + 10mv (lt1719s8) (lt1719s6) l l +v s C 0.4 v + C 0.4 v v v ol output low voltage i sink = 10ma, v in = v trip C C 10mv l 0.4 v t pd20 propagation delay v overdrive = 20mv (note 9) v ee = 0v(lt1719s8) v C = 0v(lt1719s6) l 4.5 6.5 8.0 ns ns v overdrive = 20mv, v ee = C5v (lt1719s8 only) 4.2 ns t pd5 propagation delay v overdrive = 5mv (notes 9, 10) v ee = 0v(lt1719s8) v C = 0v(lt1719s6) l 710 13 ns ns t skew propagation delay skew (note 11) 0.5 1.5 ns t r output rise time 10% to 90% 2.5 ns t f output fall time 90% to 10% 2.2 ns t jitter output timing jitter v in = 1.2v p-p (6dbm), z in = 50 t pd + f = 20mhz t pd C 15 11 ps rms ps rms f max maximum toggle frequency v overdrive = 50mv, +v s or v + = 3v v overdrive = 50mv, +v s or v + = 5v 70 62.5 mhz mhz t off turn-off delay time to z out 10k 75 ns t on wake-up delay time to v oh or v ol , i load = 1ma 350 ns i cc positive input stage supply current + v s = v cc = 5v, v ee = C5v l 1 2.2 ma (lt1719s8 only) + v s = v cc = 3v, v ee = 0v l 0.9 1.8 ma i ee negative input stage supply current + v s = v cc = 5v, v ee = C5v l C4.8 C2.6 ma (lt1719s8 only) + v s = v cc = 3v, v ee = 0v l C3.8 C2.2 ma the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cm = 1v, v shdn = 0.5v, v overdrive = 20mv, c out = 10pf and for the lt1719s8 v cc = +v s = 5v and v ee = C5v, for the lt1719s6 v + = 5v, v C = 0v, unless otherwise speci? ed.
lt1719 4 1719fa symbol parameter conditions min typ max units i s positive output stage supply current + v s = v cc = 5v, v ee = C5v l 4.2 8 ma (lt1719s8 only) v s = v cc = 3v, v ee = 0v l 3.3 6 ma i + supply current (lt1719s6) v + = 5v l 4.6 9 ma v + = 3v l 4.2 7 ma i shdn5 shutdown pin current +v s or v + = 5v l C300 C110 C30 a i shdn3 shutdown pin current +v s or v + = 3v l C200 C80 C20 a i ccs i ss i ees i + s i ccso i sso i eeo i + o disabled supply currents (lt1719s8) (lt1719s8) (lt1719s8) (lt1719s6) (lt1719s8) (lt1719s8) (lt1719s8) (lt1719s6) +v s = 6v, v cc = 5v, v ee = C5v v shdn = +v s C 0.5v l l l C30 0.2 7 C0.2 30 50 a a a v + = 6v, v shdn = +v s C 0.5v l 780 a +v s = 6v, v cc = 5v, v ee = C5v shutdown pin open l l l C20 0.1 0.1 0.1 20 20 a a a v + = 6v, shutdown pin open l 0.2 40 a electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cm = 1v, v shdn = 0.5v, v overdrive = 20mv, c out = 10pf and for the lt1719s8 v cc = +v s = 5v and v ee = C5v, for the lt1719s6 v + = 5v, v C = 0v, unless otherwise speci? ed. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: if one input is within these common mode limits, the other input can go outside the common mode limits and the output will be valid. note 3: the lt1719 comparator includes internal hysteresis. the trip points are the input voltage needed to change the output state in each direction. the offset voltage is de? ned as the average of v trip + and v trip C , while the hysteresis voltage is the difference of these two. note 4: the lt1719s8 common mode rejection ratio is measured with v cc = 5v, v ee = C 5v and is de? ned as the change in offset voltage measured from v cm = C5.1v to v cm = 3.8v, divided by 8.9v. note 5: the lt1719s6 common mode rejection ratio is measured with v + = 5v and is de? ned as the change in offset voltage measured from v cm = C0.1v to v cm = 3.8v, divided by 3.9v. note 6: the lt1719s8 power supply rejection ratio is measured with v cm = 1v and is de? ned as the worst of: the change in offset voltage from v ee = C 5.5v to v ee = 0v divided by 5.5v, or the change in offset voltage from v cc = +v s = 2.7v to v cc = +v s = 6v (with v ee = 0v) divided by 3.3v. note 7: the lt1719s6 power supply rejection ratio is measured with v cm = 1v and is de? ned as the change in offset voltage measured from v + = 2.7v to v + = 6v, divided by 3.3v. note 8: because of internal hysteresis, there is no small-signal region in which to measure gain. proper operation of internal circuity is ensured by measuring v oh and v ol with only 10mv of overdrive. note 9: propagation delay measurements made with 100mv steps. overdrive is measured relative to v trip . note 10: t pd cannot be measured in automatic handling equipment with low values of overdrive. the lt1719 is 100% tested with a 100mv step and 20mv overdrive. correlation tests have shown that t pd limits can be guaranteed with this test, if additional dc tests are performed to guarantee that all internal bias conditions are correct. note 11: propagation delay skew is de? ned as: t skew = |t pdlh C t pdhl |
lt1719 5 1719fa typical performance characteristics quiescent supply current vs supply voltage supply voltage, v cc = +v s or v + (v) 2.5 v os and trip point voltage (mv) 3 2 1 0 C1 C2 C3 4.0 5.0 1719 g01 3.0 3.5 4.5 5.5 6.0 v trip + v os v trip C 25c v cm = 1v v ee or v C = gnd temperature (c) C3 v os and trip point voltage (mv) C1 1 3 C2 0 2 C20 20 60 100 1719 g02 140 C40 C60 0 40 80 120 v trip + v os v trip C +v s = v cc or v + = 5v v cm = 1v v ee or v C = gnd temperature (c) C50 0 3.8 4.2 25 75 1719 g03 C0.2 C5.0 C25 0 50 100 125 C5.2 C5.4 4.0 common mode input voltage (v) +v s = v cc or v + = 5v v ee = C5v (lt1719s8) v C = gnd (lt1719s6) differential input voltage (v) C5 C7 input bias (a) C6 C4 C3 C2 1234 2 1719 g04 C5 C4 C3 C2 C1 0 5 C1 0 1 25c temperature (c) C50 supply current (ma) 100 1339 g05 050 10 8 6 4 2 0 C2 C4 C6 C25 25 75 125 v cc = +v s or v + = 5v v ee = gnd i + (lt1719s6) +i s (lt1719s8) i cc (lt1719s8) i ee (lt1719s8) supply voltage, v cc = +v s or v + (v) 0 supply currents (ma) 2 6 5 4 3 2 1 0 C1 C2 C3 1719 g06 17 3456 t a = 25c v ee = gnd i + (lt1719s6) i s (lt1719s8) i cc (lt1719s8) i ee (lt1719s8) temperature (c) C50 propagation delay (ns) 7.5 25 1719 g08 6.0 5.0 C25 0 50 4.5 4.0 8.0 7.0 6.5 5.5 75 100 125 overdrive = 5mv overdrive = 20mv 3v 5v t pdlh v cm = 1v v step = 100mv c load = 10pf v ee or v C = gnd +v s = v cc = v + 3v 5v supply voltage, +v s = v cc or v + (v) 2.5 4.0 3.5 propagation delay (ns) 5.5 5.0 t tplh t tplh t tphl t tphl 4.5 4.0 5.0 1719 g09 3.0 3.5 4.5 5.5 6.0 25c v step = 100mv overdrive = 20mv c load = 10pf v ee /v C = gnd v ee = C5v (v cc , +v s = 5.5v max ) (lt1719s8 only) output load capacitance (pf) 0 propagation delay (ns) 30 50 1719 g07 10 20 40 9 8 7 6 5 4 3 2 1 0 25c v step = 100mv overdrive = 20mv +v s = v cc or v + = 5v v ee or v C = 0v rising edge (t pdlh ) falling edge (t pdhl ) propagation delay vs supply voltage propagation delay vs temperature propagation delay vs load capacitance quiescent supply current vs temperature input current vs differential input voltage input offset and trip voltages vs supply voltage input offset and trip voltages vs temperature input common mode limits vs temperature
lt1719 6 1719fa typical performance characteristics frequency (mhz) 0 6 8 30 no load 1719 g12 4 3 10 20 40 2 5 7 9 +v s supply current (ma) 25c +v s = 5v c load = 20pf c load = 10pf output sink current (ma) 0 output voltage (v) 0.3 0.4 16 1719 g10 0.2 0.1 4 8 12 20 0.5 125c 25c 125c v cc = 2.7v +v s or v + = 5v v in = C10mv C55c output source current (ma) 0 output voltage relative to +v s (v) C0.4 C0.2 0.0 16 1719 g11 C0.6 C0.8 C1.0 4 8 12 20 125c C55c 25c 25c v cc = 2.7v +v s or v + = 5v v in = 10mv shdn pin voltage (v) v s C4 shdn pin current (a) supply currents (ma) 4 3 2 1 0 C50 C100 v s C3 v s C2 v s C1 v s 1719 g13a t a = 25c v ee = gnd +v s = v cc = 5v lt1719s8 i s i cc shdn pin voltage (v) v + C4 shdn pin current (a) supply i + current (ma) 5 4 3 2 1 0 C50 C100 v + C3 v + C2 v + C1 v + 1719 g13b t a = 25c v + = 5v lt1719s6 supply current vs frequency output high voltage vs load current output low voltage vs load current shutdown currents vs shutdown voltage shutdown currents vs shutdown voltage temperature (c) C50 wake-up delay (ns) 500 600 700 25 75 1719 g15 400 300 C25 0 50 100 125 200 100 wake-up delay vs temperature temperature (c) shutdown currents (a) 0.1 1 10 C50 25 50 75 100 125 C25 0 150 1719 g14 shutdown pin open shutdown = +v s C 0.5v +i s +i s shutdown pin current v cc = +v s = 5v v ee = C5v shutdown currents vs temperature
lt1719 7 1719fa pin functions lt1719s8 v cc (pin 1): positive supply voltage for input stage. + in (pin 2): noninverting input of comparator. Cin (pin 3): inverting input of comparator. v ee (pin 4): negative supply voltage for input stage and chip substrate. gnd (pin 5): ground. shdn (pin 6): shutdown. pull to ground to enable comparator. out (pin 7): output of comparator. +v s (pin 8): positive supply voltage for output stage. lt1719s6 Cin (pin 1): inverting input of comparator. v C (pin 2): negative supply, usually grounded. + in (pin3): noninverting input of comparator. v + (pin 4): positive supply voltage. out (pin 5): output of comparator. shdn (pin 6): shutdown. pull to ground to enable comparator.
lt1719 8 1719fa test circuits v trip test circuit + C + C + C C + dut lt1719 bandwidth-limited triangle wave ~ 1khz, v cm 7.5v ltc203 1/2 lt1112 50 100k 100k 2.4k 10nf 1f 0.15f 1/2 lt1638 1/2 lt1638 100k 100k 200k 10k 10k 1000 v hyst 1000 v trip + 1000 v trip C 1000 v os 0.1f 50 50k v cm v cc + C 1/2 lt1112 1719 tc01 10nf 1f notes: lt1638, lt1112, ltc203s are powered from 15v. 200k pull-down protects ltc203 logic inputs when dut is not powered 15 3 2 14 16 9 1 8 10 6 7 11 ltc203 2 14 15 3 1 8 16 9 7 11 10 6 response time test circuit C + C3v C100mv 1 8 7 6(6) 2 3 5 4 C5v pulse in 0v 0v 50 1n5711 400 130 25 50 +v s C v cm (v + C v cm ) v cc C v cm v ee C v cm Cv cm 50k dut lt1719s8 25 0.1f 1719 tc02 10 scope probe (c in 10pf) 0.01f 0.01f 750 2n3866 v1* *v1 = C1000 ? (overdrive + v trip + ) note: rising edge test shown. for falling edge, reverse lt1719 inputs
lt1719 9 1719fa applications information figure 1. variety of so-8 power supply con? gurations when either input signal falls below the negative com- mon mode limit, the internal pn diode formed with the substrate can turn on, resulting in signi? cant current ? ow through the die. an external schottky clamp diode between the input and the negative rail can speed up re- covery from negative overdrive by preventing the substrate diode from turning on. when both input signals are below the negative common mode limit, phase reversal protection circuitry prevents false output inversion to at least C 400mv common mode. however, the offset and hysteresis in this mode will increase dramatically, to as much as 15mv each. the input bias currents will also increase. when both input signals are above the positive common mode limit, the input stage will get debiased and the output polarity will be random. however, the internal hysteresis will hold the output to a valid logic level. when at least one of the inputs returns to within the common mode limits, recovery from this state can take as long as 1s. power supply con? gurations (so-8 package) the lt1719s8 has separate supply pins for the input and output stages that allow ? exible operation, accommodating separate voltage ranges for the analog input and the output logic. of course, a single 3v/5v supply may be used by tying + v s and v cc together as well as gnd and v ee . the minimum voltage requirement can be simply stated as both the output and the input stages need at least 2.7v and the v ee pin must be equal to or less than ground. the following rules must be adhered to in any con? guration: 2.7v (v cc C v ee ) 10.5v 2.7v (+ v s C gnd) 6v (+v s C v ee ) 10.5v v ee ground although the ground pin need not be tied to system ground, most applications will use it that way. figure 1 shows three common con? gurations. the ? nal one is uncommon, but it will work and may be useful as a level translator; the input stage is run from C 5.2v and ground while the output stage is run from 3v and ground. in this case the com- mon mode input voltage range does not include ground, so it may be helpful to tie v cc to 3v anyway. conversely, v cc may also be tied below ground, as long as the above rules are not violated. input voltage considerations the lt1719 is speci? ed for a common mode range of C100mv to 3.8v when used with a single 5v supply. a more general consideration is that the common mode range is 100mv below v ee /v C to 1.2v below v cc /v + . the criterion for this common mode limit is that the output still responds correctly to a small differential input signal. if one input is within the common mode limit, the other input signal can go outside the common mode limits, up to the absolute maximum limits, and the output will retain the correct polarity. C + v ee v cc 2.7v to 6v +v s gnd single supply C + v ee v cc 5v C5v 3v +v s gnd 5v in , 3v out C + v ee v cc 10v 5v +v s gnd 10v in , 5v out C + v ee v cc C5.2v 3v +v s gnd 1719 f01 front end entirely negative lt1719s8 lt1719s8 lt1719s8 lt1719s8
lt1719 10 1719fa applications information the propagation delay does not increase signi? cantly when driven with large differential voltages, but with low levels of overdrive, an apparent increase may be seen with large source resistances due to an rc delay caused by the 2pf typical input capacitance. input protection the input stage is protected against damage from large differential signals, up to and beyond a differential voltage equal to the supply voltage, limited only by the absolute maximum currents noted. external input protection cir- cuitry is only needed if currents would otherwise exceed these absolute maximums. the internal catch diodes can conduct current up to these rated maximums without latchup, even when the supply voltage is at the absolute maximum rating. the lt1719 input stage has general purpose internal esd protection for the human body model. for use as a line receiver, additional external protection may be required. as with most integrated circuits, the level of immunity to esd is much greater when residing on a printed circuit board where the power supply decoupling capacitance will limit the voltage rise caused by an esd pulse. input bias current input bias current is measured with both inputs held at 1v. as with any pnp differential input stage, the lt1719 bias current ? ows out of the device. it will go to zero on the higher of the two inputs and double on the lower of the two inputs. with more than two diode drops of differential input voltage, the lt1719s input protection circuitry activates, and current out of the lower input will increase an additional 30% and there will be a small bias current into the higher of the two input pins, of 4a or less. see the typical performance curve input current vs differential input voltage. high speed design considerations application of high speed comparators is often plagued by oscillations. the lt1719 has 4mv of internal hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mv. however, with the 2v/ns slew rate of the lt1719 outputs, a 4mv step can be created at a 100 input source with only 0.02pf of output to input coupling. the lt1719s pinout has been arranged to minimize problems by placing the sensitive inputs away from the outputs, shielded by the power rails. the input and output traces of the circuit board should also be separated, and the requisite level of isolation is readily achieved if a topside ground plane runs between the output and the inputs. for multilayer boards where the ground plane is internal, a topside ground or supply trace should be run between the inputs and the output. figure 2 shows a typical topside layout of the lt1719s8 on such a multilayer board. shown is the topside metal etch including traces, pin escape vias, and the land pads for an so-8 lt1719 and its adjacent x7r 10nf bypass capacitors in the 1206 case. the same principles should be used with the sot 23-6. 1719 f02 figure 2. typical topside metal for multilayer pcb layouts the ground trace from pin 5 runs under the device up to the bypass capacitor, shielding the inputs from the outputs. note the use of a common via for the lt1719 and the bypass capacitors, which minimizes interference from high frequency energy running around the ground plane or power distribution traces. the supply bypass should include an adjacent 10nf ceramic capacitor and a 2.2f tantalum capacitor no farther than 5cm away; use more capacitance on + v s if driving more than 4ma loads. to prevent oscillations, it is helpful to balance the impedance at the inverting and noninverting inputs; source impedances should be kept low, preferably 1k or less.
lt1719 11 1719fa applications information the outputs of the lt1719 are capable of very high slew rates. to prevent overshoot, ringing and other problems with transmission line effects, keep the output traces shorter than 10cm, or be sure to terminate the lines to maintain signal integrity. the lt1719 can drive dc terminations of 200 or more, but lower characteristic impedance traces can be used with series termination or ac termination topologies. shutdown control the lt1719 features a shutdown control pin for reduced quiescent current when the comparator is not needed. during shutdown, the inputs and the outputs become high impedances. the lt1719 is enabled when the shutdown input is pulled low with a threshold roughly two diode drops below + v s or v + . therefore, if driven by a standard ttl gate, a pull-up resistor should be used. because shutdown is active high, this resistor adds little power drain during shutdown. a logic high disables the comparator. the lt1719s8 logic interface is based on the output power rails, +v s and gnd. for applications that do not use the shutdown feature, it may be helpful to tie the shutdown control to ground through a 100 resistor rather than directly. this allows the shdn pin to be pulled high during debug or in-circuit test (bed of nails) so that the output node can be wiggled without damaging the low impedance output driver of the lt1719. the shutdown state is not guaranteed to be useful as a multiplexer. digital signals can have extremely fast edge rates that may be enough to momentarily activate the lt1719 output stage via internal capacitive coupling. no damage to the lt1719 will result, but this could prove deleterious to the intended recipient of the signal. the lt1719 includes a fet pull-up on the shutdown control pin (see the simpli? ed schematic) as well as other inter- nal structures to make the shutdown state current drain <<1a. shutdown is guaranteed with an open circuit on the shutdown control pin. when the shutdown control pin is driven to +v s /v + C 0.5v, the 70k linear region impedance of the pull-up fet will cause a current ? ow of 7a (typ) into the +v s /v + pin and out the shutdown pin. currents in all other power supply terminals will be <1a. power supply sequencing the lt1719s8 is designed to tolerate any power supply sequencing at system turn-on and power down. in any of the previously shown power supply con? gurations, the various supplies can activate in any order without exces- sive current drain by the lt1719. as always, the absolute maximum ratings must not be exceeded, either on the power supply terminals or the input terminals. power supply sequencing problems can occur when input signals are powered from supplies that are independent of the lt1719s supplies. for the compara- tor inputs, the signals should be powered from the same v cc and v ee supplies as the lt1719. for the shutdown input, the signal should be powered from the same +v s as the lt1719. hysteresis the lt1719 includes internal hysteresis, which makes it easier to use than many other similar speed comparators. the input-output transfer characteristic is illustrated in figure 3 showing the de? nitions of v os and v hyst based upon the two measurable trip points. the hysteresis band makes the lt1719 well behaved, even with slowly moving inputs. figure 3. hysteresis i/o characteristics v hyst (= v trip + C v trip C ) v hyst /2 v ol 1719 f03 v oh v trip C v trip + v in = v in + C v in C v trip + + v trip C 2 v os = v out 0
lt1719 12 1719fa on the common mode and power supply dependence of the hysteresis voltage. additional hysteresis may be added externally. the rail- to-rail outputs of the lt1719 make this more predictable than with ttl output comparators due to the lt1719s small variability of v oh (output high voltage). to add additional hysteresis, set up positive feedback by adding additional external resistor r3 as shown in figure 4. resistor r3 adds a portion of the output to the threshold set by the resistor string. the lt1719 pulls the outputs to + v s and ground to within 200mv of the rails with light loads, and to within 400mv with heavy loads. for the load of most circuits, a good model for the voltage on the right side of r3 is 300mv or +v s C 300mv, for a total voltage swing of (+v s C 300mv) C (300mv) = +v s C 600mv. the exact amount of hysteresis will vary from part to part as indicated in the speci? cations table. the hysteresis level will also vary slightly with changes in supply voltage and common mode voltage. a key advantage of the lt1719 is the signi? cant reduction in these effects, which is im- portant whenever an lt1719 is used to detect a threshold crossing in one direction only. in such a case, the relevant trip point will be all that matters, and a stable offset volt- age with an unpredictable level of hysteresis, as seen in competing comparators, is useless. the lt1719 is many times better than prior comparators in these regards. in fact, the cmrr and psrr tests are performed by check- ing for changes in either trip point to the limits indicated in the speci? cations table. because the offset voltage is the average of the trip points, the cmrr and psrr of the offset voltage is therefore guaranteed to be at least as good as those limits. this more stringent test also puts a limit C + lt1719s8 input 1719 f04 r2 v ref r3 r1 figure 4. additional external hysteresis applications information
lt1719 13 1719fa ? + lt1719s8 1719 f05 r2 ? v ref v th r3 +v s 2 v average = r1 figure 5. model for additional hysteresis calculations with this in mind, calculation of the resistor values needed is a two-step process. first, calculate the value of r3 based on the additional hysteresis desired, the output voltage swing and the impedance of the primary bias string: r3 = (r1 ?? r2)(+v s C 0.6v)/(additional hysteresis) additional hysteresis is the desired overall hysteresis less the internal 4mv hysteresis. the second step is to recalculate r2 to set the same av- erage threshold as before. the average threshold before was set at v th = (v ref )(r1)/(r1 + r2). the new r2 is calculated based on the average output voltage (+v s /2) and the simpli? ed circuit model in figure 5. to assure that the comparators noninverting input is, on average, the same v th as before: r2 ? = (v ref C v th )/(v th /r1 + [v th C (+v s )/2]/r3) for additional hysteresis of 10mv or less, it is not un- common for r2 ? to be the same as r2 within 1% resistor tolerances. this method will work for additional hysteresis of up to a few hundred millivolts. beyond that, the impedance of r3 is low enough to effect the bias string, and adjustment of r1 may also be required. note that the currents through the r1/r2 bias string should be many times the input currents of the lt1719. for 5% accuracy, the current must be at least 20 times the input current, more for higher accuracy. this illustration used an lt1719s8; with an lt1719s6 the same procedure is used with v + substituted for +v s . applications information
lt1719 14 1719fa figure 6a shows the standard ttl to positive ecl (pecl) resistive level translator. this translator cannot be used for the lt1719, or with cmos logic, because it depends on the 820 resistor to limit the output swing (v oh ) of the all-npn ttl gate with its so-called totem-pole output. the lt1719 is fabricated in a complementary bipolar process and the output stage has a pnp driver that pulls the output nearly all the way to the supply rail, even when sourcing 10ma. interfacing the lt1719 to ecl the lt1719 comparators can be used in high speed ap- plications where emitter-coupled logic (ecl) is deployed. to interface the output of the lt1719 to ecl logic inputs, standard ttl/cmos to ecl level translators such as the 10h124, 10h424 and 100124 can be used. these com- ponents come at a cost of a few nanoseconds additional delay as well as supply currents of 50ma or more, and are only available in quads. a faster, simpler and lower power translator can be constructed with resistors as shown in figure 6. applications information figure 6 5v 5v 180 do not use for lt1719 level translation. see text 270 820 10kh/e r2 +v s or v + r3 r1 10kh/e 100k/e +v s or v + 5v or 5.2v 4.5v r1 510 620 r2 180 180 r3 750 510 (a) standard ttl to pecl translator (b) lt1719 output to pecl translator lsttl lt1719 r2 v ecl 3v r3 r4 r1 10kh/e 100k/e v ecl 5v or 5.2v 4.5v r1 300 330 r2 180 180 r3 omit 1500 (c) 3v lt1719 output to pecl translator lt1719 r4 560 1000 r4 v ecl +v s or v + r3 1719 f06 r2 r1 ecl family 10kh/e v ecl C5.2v r1 560 270 +v s or v + 5v 3v r2 270 510 r3 330 300 (d) lt1719 output to standard ecl translator lt1719 r4 1200 330 100k/e C4.5v 680 330 5v 3v 270 390 300 270 1500 430
lt1719 15 1719fa figure 6b shows a three resistor level translator for inter- facing the lt1719 to ecl running off the same supply rail. no pull-down on the output of the lt1719 is needed, but pull-down r3 limits the v ih seen by the pecl gate. this is needed because ecl inputs have both a minimum and maximum v ih speci? cation for proper operation. resis- tor values are given for both ecl interface types; in both cases it is assumed that the lt1719 operates from the same supply rail. figure 6c shows the case of translating to pecl from an lt1719 powered by a 3v supply rail. again, resistor values are given for both ecl interface types. this time four resistors are needed, although with 10kh/e, r3 is not needed. in that case, the circuit resembles the standard ttl translator of figure 6a, but the function of the new resistor, r4, is much different. r4 loads the lt1719 output when high so that the current ? owing through r1 doesnt forward bias the lt1719s internal esd clamp diode. although this diode can handle 20ma without damage, normal operation and performance of the output stage can be impaired above 100a of forward current. r4 prevents this with the minimum additional power dissipation. finally, figure 6d shows the case of driving standard, negative-rail, ecl with the lt1719. resistor values are given for both ecl interface types and for both a 5v and 3v lt1719 supply rail. again, a fourth resistor, r4 is needed to prevent the low state current from ? owing out of the lt1719, turning on the internal esd/substrate diodes. resistor r4 again prevents this with the minimum additional power dissipation. of course, in the so-8 package, if the v ee of the lt1719 is the same as the ecl negative supply, the gnd pin can be tied to it as well and + v s grounded. then the output stage has the same power rails as the ecl and the circuits of figure 6b can be used. for all the dividers shown, the output impedance is about 110. this makes these fast, less than a nanosecond, with most layouts. avoid the temptation to use speedup capacitors. not only can they foul up the operation of the ecl gate because of overshoots, they can damage the ecl inputs, particularly during power-up of separate supply con? gurations. similar circuits can be used with the emerging lvecl and lvpecl standards. the level translator designs shown assume one gate load. multiple gates can have signi? cant i ih loading, and the transmission line routing and termination issues also make this case dif? cult. ecl, and particularly pecl, is valuable technology for high speed system design, but it must be used with care. with less than a volt of swing, the noise margins need to be evaluated carefully. note that there is some degradation of noise margin due to the 5% resistor selections shown. with 10kh/e, there is no temperature compensation of the logic levels, whereas the lt1719 and the circuits shown give levels that are stable with temperature. this will lower the noise margin over temperature. in some con? gurations it is possible to add compensation with diode or transistor junctions in series with the resistors of these networks. for more information on ecl design, refer to the eclips data book (dl140), the 10kh system design handbook (hb205) and pecl design (an1406), all from motorola, now on semiconductor. applications information
lt1719 16 1719fa circuit description the block diagram of the lt1719 is shown in figure 7. the circuit topology consists of a differential input stage, a gain stage with hysteresis and a complementary com- mon-emitter output stage. all of the internal signal paths utilize low voltage swings for high speed at low power. the input stage topology maximizes the input dynamic range available without requiring the power, complexity and die area of two complete input stages such as are found in rail-to-rail input comparators. with a single 2.7v supply, the lt1719 still has a respectable 1.6v of input common mode range. the differential input volt- age range is rail-to-rail, without the large input currents found in competing devices. the input stage also features phase reversal protection to prevent false outputs when the inputs are driven below the C100mv common mode voltage limit. the internal hysteresis is imp lemented by positive, nonlin- ear feedback around a second gain stage. until this point, the signal path has been entirely differential. the signal path is then split into two drive signals for the upper and lower output transistors. the output transistors are con- nected common emitter for rail-to-rail output operation. the schottky clamps limit the output voltages at about 300mv from the rail, not quite the 50mv or 15mv of linear technologys rail-to-rail ampli?ers and other products. but the output of a comparator is digital, and this output stage can drive ttl or cmos directly. it can also drive ecl, as described earlier, or analog loads as demonstrated in the applications to follow. the bias conditions and signal swings in the output stage are designed to turn their respective output transistors off faster than on. this helps minimize the surge of current from +v s /v + to ground that occurs at transitions, to minimize the frequency-dependent increase in power consumption. the frequency dependence of the supply current is shown in the typical performance characteristics. speed limits the lt1719 comparator is intended for high speed ap- plications, where it is important to understand a few limitations. these limitations can roughly be divided into applications information out gnd or v C +v s or v + C + C + C + C + +in Cin a v1 v cc or v + v ee or v C shutdown a v2 nonlinear stage 1719 f07 + + bias contol figure 7. lt1719 block diagram
lt1719 17 1719fa three categories: input speed limits, output speed limits, and internal speed limits. there are no signi?cant input speed limits except the shunt capacitance of the input nodes. if the 2pf typical input nodes are driven, the lt1719 will respond. the output speed is constrained by two mechanisms, the ? rst of which is the slew currents available from the output transistors. to maintain low power quiescent operation, the lt1719 output transistors are sized to deliver 25ma to 45ma typical slew currents. this is suf?cient to drive small capacitive loads and logic gate inputs at extremely high speeds. but the slew rate will slow dramatically with heavy capacitive loads. because the propagation delay (t pd ) de?nition ends at the time the output voltage is halfway between the supplies, the ?xed slew current makes the lt1719 faster at 3v than 5v with large capacitive loads and suf? cient input overdrive. another manifestation of this output speed limit is skew, the difference between t pd + and t pd C . the slew currents of the lt1719 vary with the process variations of the pnp and npn transistors, for rising edges and falling edges respectively. the typical 0.5ns skew can have either polarity, rising edge or falling edge faster. again, the skew will increase dramatically with heavy capacitive loads. a separate output speed limit is the clamp turnaround. the lt1719 output is optimized for fast initial response, with some loss of turnaround speed, limiting the toggle frequency. the output transistors are idled in a low power state once v oh or v ol is reached, by detecting the schottky clamp action. it is only when the output has slewed from the old voltage to the new voltage, and the clamp circuitry has settled, that the idle state is reached and the lt1719 is fully ready to toggle again. this is typically 8ns for each direction, resulting in a maximum toggle frequency of 62.5mhz. with higher frequencies, dropout and runt pulses can result. increases in capacitive load will increase the time needed for slewing due to the limited slew currents and the maximum toggle frequency will decrease further. for high toggle frequency applications, consider the lt1394, whose linear output stage can toggle at 100mhz typical. the internal speed limits manifest themselves as disper- sion. all comparators have some degree of dispersion, de?ned as a change in propagation delay versus input overdrive. the propagation delay of the lt1719 will vary with overdrive, from a typical of 4.5ns at 20mv overdrive to 7ns at 5mv overdrive (typical). the lt1719s primary source of dispersion is the hysteresis stage. as a change of polarity arrives at the gain stage, the positive feedback of the hysteresis stage subtracts from the overdrive avail- able. only when enough time has elapsed for a signal to propagate forward through the gain stage, backwards through the hysteresis path and forward through the gain stage again, will the output stage receive the same level of overdrive that it would have received in the absence of hysteresis. the lt1719s8 is several hundred picoseconds faster when v ee = C 5v, relative to single supply operation. this is due to the internal speed limit; the gain stage operates between v ee and +v s , and it is faster with higher reverse voltage bias due to reduced silicon junction capacitances. in many applications, as shown in the following examples, there is plenty of input overdrive. even in applications pro- viding low levels of overdrive, the lt1719 is fast enough that the absolute dispersion of 2.5ns (= 7 C 4.5) is often small enough to ignore. the gain and hysteresis stage of the lt1719 is simple, short and high speed to help prevent parasitic oscillations while adding minimum dispersion. this internal self-latch can be usefully exploited in many applications because it occurs early in the signal chain, in a low power, fully differential stage. it is therefore highly immune to disturbances from other parts of the circuit, such as the output, or on the supply lines. once a high speed signal trips the hysteresis, the output will respond, after a ?xed propagation delay, without regard to these external in?uences that can cause trouble in nonhysteretic comparators. applications information
lt1719 18 1719fa C + C + c1 lt1719 a1 lt1636 v cc 2.7v to 6v 2k 620 220 1mhz to 10mhz crystal (at-cut) 100k 200k 200k 1720 f07 1.8k 2k 1k 0.1f 0.1f 0.1f output v cc ground case figure 8. crystal oscillator with a forced 50% duty cycle applications information v trip test circuit the input trip points test circuit uses a 1khz triangle wave to repeatedly trip the comparator being tested. the lt1719 output is used to trigger switched capacitor sampling of the triangle wave, with a sampler for each direction. because the triangle wave is attenuated 1000:1 and fed to the lt1719s differential input, the sampled voltages are therefore 1000 times the input trip voltages. the hysteresis and offset are computed from the trip points as shown. crystal oscillator a simple crystal oscillator using an lt1719 is shown on the ? rst page of this data sheet. the 2k-620 resistor pair set a bias point at the comparators noninverting input. the 2k-1.8k-0.1f path sets the inverting input node at an appropriate dc average level based on the output. the crystals path provides resonant positive feedback and stable oscillation occurs. although the lt1719 will give the correct logic output when one input is outside the common mode range, additional delays may occur when it is so operated, opening the possibility of spurious operating modes. therefore, the dc bias voltages at the inputs are set near the center of the lt1719s common mode range and the 220 resistor attenuates the feedback to the noninverting input. the circuit will operate with any at-cut crystal from 1mhz to 10mhz over a 2.7v to 6v sup- ply range. as the power is applied, the circuit remains off until the lt1719 bias circuits activate, at a typical v cc of 2v to 2.2v (25c), at which point the desired frequency output is generated. the output duty cycle of this circuit is roughly 50%, but it is affected by resistor tolerances and to a lesser extent, by comparator offsets and timings. if a 50% duty cycle is required, the circuit of figure 8 forces a 50% duty cycle. crystals are narrow-band elements, so the feedback to the noninverting input is a ? ltered analog version of the square wave output. changing the noninverting reference level can therefore vary the duty cycle. c1 operates as in the previous example while a1 compares a band-limited version of the output and biases c1s negative input. c1s only degree of freedom to respond is variation of pulse width; hence the output is forced to 50% duty cycle. again, the circuit operates from 2.7v to 6v. there is a slight duty cycle dependence on comparator loading, so minimal capacitive and resistive loading should be used in critical applications.
lt1719 19 1719fa Cin +in v ee (v C ) 1719 ss output gnd (v C ) +v s (v + ) v cc (v + ) 150 150 to bias sources 15k shdn simplified schematic
lt1719 20 1719fa .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.50 8 ) 45 0 ? 8 typ .00 8 ? .010 (0.203 ? 0.254) so 8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.4 8 3) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3. 8 10 ? 3.9 88 ) note 3 8 7 6 5 .1 8 9 ? .197 (4. 8 01 ? 5.004) note 3 .22 8 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) package description
lt1719 21 1719fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1.50 ? 1.75 (note 4) 2. 8 0 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0. 8 0 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3. 8 5 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref package description s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636)
lt1719 22 1719fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2000 lt 0809 rev a ? printed in usa related parts typical application part number description comments lt1016 ultrafast precision comparator industry standard 10ns comparator lt1116 12ns single supply ground-sensing comparator single supply version of lt1016 lt1394 7ns, ultrafast, single supply comparator 6ma single supply comparator lt1671 60ns, low power, single supply comparator 450a single supply comparator lt1713/lt1714 single/dual 7ns, rail-to-rail comparator rail-to-rail inputs and outputs lt1720/lt1721 dual/quad 4.5ns, single supply 3v/5v comparator dual/quad comparator similar to the lt1719 high performance sine wave to square wave converter propagation delay of comparators is typically speci? ed for a 100mv step with some fraction of that for overdrive. but in many signal processing applications, such as in com- munications, the goal is to convert a sine wave, such as a carrier, to a square wave for use as a timing clock. the desired behavior is for the output timing to be dependent on the input timing only. no phase shift should occur as a function of the input amplitude, which would result in am to fm conversion. the circuit of figure 9a is a simple lt1719s8-based sine wave to square wave converter. the 5v supplies on the input allow very large swing inputs, while the 3v logic supply keeps the output swing small to minimize cross talk. figure 9b shows the time delay vs input amplitude with a 10mhz sine wave. the lt1719 delay changes just 0.65ns over the 26db amplitude range; 2.33 at 10mhz. the delay is particularly ? at yielding excellent am rejection figure 9a. lt1719-based sine wave to square wave converter from 0dbm to 15dbm. if a 2:1 transformer is used to drive the input differentially, this exceptionally ? at zone spans C5dbm to 10dbm, a common range for rf signal levels. similar delay performance is achieved with input frequen- cies as high as 50mhz. there is, however, some additional encroachment into the central ? at zone by both the small amplitude and large amplitude variations. with small input signals, the hysteresis and dispersion make the lt1719 act like a comparator with a 12mv hysteresis span. in other words, a 12mv p-p sine wave at 10mhz will barely toggle the lt1719, with 90 of phase lag or 25ns additional delay. above 5v p-p at 10mhz, the lt1719 delay starts to decrease due to internal capacitive feed-forward in the input stage. unlike some comparators, the lt1719 will not falsely an- ticipate a change in input polarity, but the feed-forward is enough to make a transition propagate through the lt1719 faster once the input polarity does change. C + lt1719s8 50 1719 f09a sine wave input square wave output 5v C5v 3v input amplitude (dbm) C5 0 time delay (ns) 1 2 3 4 5 0 51015 1719 f09b 20 25 632mv p-p 2v p-p 6.32v p-p 25c v cc = 5v v ee = C5v +v s = 3v 10mhz figure 9b. time delay vs sine wave input amplitude

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